1. Field of the Invention
The present invention relates to a dynamic memory of the integrated-circuit type and is also concerned with a method for the fabrication of said memory.
2. Description of the Prior Art
The memories under consideration in this invention are based on the principle of capacitive data storage. In a memory of this type, a memory cell comprises a transistor in which the gate is connected to a so-called word line and in which the two main electrodes are connected on the one hand to a data storage capacitor and on the other hand to a data transfer line or so-called bit line. The transfer line serves either to read data written in the memory cell or to write data. For the reading operation, the memory cell transistor receives a pulse on its gate via the word line, whereupon said transistor is turned-on, the capacitor is discharged and the information contained therein is collected by the bit line. For the writing operation, the reverse operation takes place. Thus an item of information to be recorded is present on the bit line, the transistor gate receives a pulse via its word line, the transistor is turned-on and the capacitor is charged. Moreover, since the reading operation is destructive (destructive readout), this step is usually followed by re-writing of data in the memory cell.
The disadvantage of dynamic memories involving capacitive data storage lies in the fact that the information stored in a memory cell undergoes "fading" or decay over a period of time. In order to overcome this difficulty, it is necessary in the first place to refresh the information contained in the memory cells and in the second place to adopt a preventive step which consists in increasing the storage capacitance of each memory cell. As the storage capacitance is raised to higher values, so the duty cycle or frequency of the memory refresh operation an be lowered. Furthermore, at the time of operations which involve reading from and writing into a memory cell, turn-on of the transistor is equivalent to putting the storage capacitor in parallel with the bit line capacitor. It should in fact be noted that, by reason of their very length, the bit lines which extend over the entire memory plane constitute capacitors, a capacitor being located between the bit line and the ground connection of the semiconductor substrate in which the memory is integrated. A generally accepted principle is that the information contained in a memory cell capacitor is still readable when the memory cell capacitance exceeds one-fifteenth of the bit-line capacitance. Beyond this level, transmission noises have an adverse effect on reading significance.
The capacitors of each memory cell are formed by opposition of two conducting layers separated by an insulating layer. In order to increase the capacitance of the memory cells, it has been proposed to spread the capacitance practically over the entire surface of the memory cell. This technique, however, is subject to a limitation in regard to the increase in integration density. In fact, if the number of memory cells per unit surface area increases, the value of capacitance assigned to each cell and attained in this manner will be reduced accordingly. Instead of spreading the capacitance over the top surface of the memory cell, it has even been proposed to cut trenches around the entire memory cell and to form capacitors by opposition of conducting layers applied on the walls and between the walls of these trenches. However, this technique cannot readily be carried out in actual practice. Its effectiveness increases as the trenches are cut to a greater depth but this also gives rise to greater difficulties.
Finally, at the time of utilization of the memory, the speed at which reading or writing orders can be executed depends on the speed at which the word lines are capable of transmitting pulses to the transistors concerned. In order to satisfy requirements of simplification of the fabrication process, the word lines coincide with the gate electrodes of the transistors and consist of silicon strips separated from the conduction channels of the transistors by a thin gate oxide layer. The silicon of these connecting leads is never perfectly conductive and the word lines are therefore resistive. Since they are also capacitive by virtue of their environment in the same manner as the bit lines, said word lines induce the presence of propagation time constants. These time constants impose a limitation on the speed of execution of reading and writing operations. In order to overcome this additional drawback, one expedient which has been considered in the prior art consists in adding a metallic line having very low resistance above and opposite to each word line with a view to connecting the silicon gate at uniform intervals. The memory cells thus receive the reading or writing orders at higher speeds than would have been the case if these orders had emanated from the gate lead itself. The disadvantage of this arrangement is that it entails the need to provide lines at the top of the memory for repeating the word lines. As in all other operations in a fabrication process, this additional operation makes a further contribution to a reduction in efficiency of production of memories.